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How set block parameter over Zynq AXIS Lite bus?
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I need to change some parameters inside HDL Coder blocks during the execution (for example the value of the costant, HDL Counter, Compare To Constant,...) with the AXI4-Lite bus after the creation of the IP Core for Vivado. How can i do it? maybe with the ExportedGlobal declaration for the variables used?
Kiran Kintali on 22 May 2022
Generate DUT Ports for Tunable Parameters
Tunable parameters that you use to adjust your model behavior during simulation can map to top-level DUT ports in your generated HDL code. HDL Coder™ generates one DUT port per tunable parameter.
You can generate a DUT port for a tunable parameter by using it in one of these blocks:
These blocks with the tunable parameter can be at any level of the DUT hierarchy, including within a model reference.