Xilinx System Generator error with storage container type
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George Vardakis on 24 May 2022
Commented: George Vardakis on 25 May 2022
I have a System Generator design a Vector FFT block with a Real/Imaginary part sample length of 16, and an SSR parameter of 32. My goal is to generate a Xilinx IP core which will take in multiple samples per clock cycle, drive them through the vector FFT block and output them in a similar fashion. I would also like to have the interfaces of the final IP core to be AXI stream interfaces. My current design takes in 32 samples per cycle, with each complex sample comprising of 32 bits so a total of 1024 bits of input per cycle. The design is depicted below. The parts before and after the FFT block attempt to convert the scalar input to vector input for the FFT, and the inverse. The problem is that when i try to generate it i get an error (also depicted below) because Simulink complains about the 1024 bit length of the input to the output Gateway block. I haven't been able to figure out how to solve this, so any ideas would be appreciated
Thank you for your time
Bharath Venkataraman on 24 May 2022
Xilinx System Generator is not a MathWorks product. I recommend reaching out directly to Xilinx for troubleshooting support with this issue.
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