signal over lapping in Down sampler output for ZYNQ FPGA
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muhammad ahmad on 17 Jun 2022
Commented: Bharath Venkataraman on 21 Jun 2022
I am trying to down sample a 4 MHz signal while the decimated output downsamples the signl in a way that signals of each 1 MHz is appeared in that sameband how can be this output changed dothat all the signlas in the 4 MHz band are represented in 1 MHz
Bharath Venkataraman on 17 Jun 2022
Are you trying to implement a chaneelizer? If so, here is the behavioral version in DSP System Toolbox and its HDL equivalent.
Bharath Venkataraman on 21 Jun 2022
I may not be the best person to help, so I suggest that you reach out to MathWorks support. They will be able to guide you to the right person.
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