Latches inferred from HDL code generated from m-code switch statement

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Hello,
I am trying to synthesize Verilog that I have generated (via HDL Coder) from a subsystem. The subsystem contains a custom matlab function, which itself contains an outer and nested switch statement. The synthesis tool throws a warning, saying that it has inferred latches in the HDL corresponding to the matlab function's outer switch statement.
Upon inspection of the HDL, it appears that the output of the outer switch statement is not assigned in all cases, resulting in the inferred latches. The Verilog cases missing an output assignment are those of an m-code case that contains multiple check values and a nested switch statement. Instead of 'unrolling' the case, i.e. replicating the nested switch statement under 3 single-check-value cases, HDL coder seems to 'factor out' the nested statement, placing it in an if-statement below the outer switch statement. Then when those cases are met, it sets a flag guard1 in the outer switch statement, signaling for the nested switch statement to run below.
While I believe this code still technically ensures the output val is always assigned, it does not do so all w/in the body of the outer swtich statement, and so still results in inferred latches.
Matlab function:
function y = fcn(x0, x1)
y = ufi(0, 4, 0);
switch x0
case 0
y(:) = 0;
case {1, 2, 3} % multiple check-values
switch x1 % nested switch statement
case 0
y(:) = 1;
case 1
y(:) = 2;
otherwise
y(:) = 3;
end
otherwise
y(:) = 4;
end
end
Verilog code generated from subsystem containing only the above function (with my own comments pointing out cases):
// -------------------------------------------------------------
//
// File Name: hdlsrc\m_function_hdl_coder_exps\multiple_vals_nested_switch.v
//
// Generated by MATLAB 9.11 and HDL Coder 3.19
//
//
// -- -------------------------------------------------------------
// -- Rate and Clocking Details
// -- -------------------------------------------------------------
// Model base rate: 1
// Target subsystem base rate: 1
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: multiple_vals_nested_switch
// Source Path: m_function_hdl_coder_exps/multiple_vals_nested_switch
// Hierarchy Level: 0
//
// -------------------------------------------------------------
module multiple_vals_nested_switch
(x0,
x1,
y);
input [3:0] x0; // ufix4
input [3:0] x1; // ufix4
output [3:0] y; // ufix4
reg [3:0] fcn_out1; // ufix4
reg guard1;
always @(x0, x1) begin
guard1 = 1'b0;
case ( x0) // OUTER SWITCH STATEMENT
4'b0000 :
begin
fcn_out1 = 4'b0000;
end
4'b0001 :
begin
guard1 = 1'b1; // DOES NOT ASSIGN VALUE TO fcn_out1
end
4'b0010 :
begin
guard1 = 1'b1; // DOES NOT ASSIGN VALUE TO fcn_out1
end
4'b0011 :
begin
guard1 = 1'b1; // DOES NOT ASSIGN VALUE TO fcn_out1
end
default :
begin
fcn_out1 = 4'b0100;
end
endcase
if (guard1) begin
case ( x1) // the 'factored out' nested switch statement
4'b0000 :
begin
fcn_out1 = 4'b0001;
end
4'b0001 :
begin
fcn_out1 = 4'b0010;
end
default :
begin
fcn_out1 = 4'b0011;
end
endcase
end
end
assign y = fcn_out1;
endmodule // multiple_vals_nested_switch
I did some experiments generating HDL from the attached model m_function_hdl_coder_exps.slx, and it seems like this behavior, i.e. factoring out the nested switch statement into an if(guard1) block below, only occurs when:
  1. there is a case in the outer switch statement that checks for multiple values, and
  2. that case has a nested switch statement (possibly other structures as well, but I only checked for the switch statement)
I have called this the 'multiple_vals_nested_switch' subsystem in the model provided. Note: the code is the same regardless of whether the function is in-lined or not. I also generated VHDL and saw the same behavior there as well.
Latch-inferring HDL was not generated from a m-code switch statement containing a
  1. case with multiple check-values, but no nested structure (only simple assigment) -- the 'multiple_vals_no_nested_switch' subsystem
  2. case with single check-value, but nested switch statement -- the 'single_val_nested_switch' subsystem
The obvious workaround is to 'unroll' the multiple cases myself in the m-code, but I wanted to post what I'm seeing here to a) determine if it's reproducible, and b) ask if it's an issue that can be fixed in the future.
Thanks,
Ben

Answers (1)

Kiran Kintali
Kiran Kintali on 5 Oct 2022
Thank you for the reproduction model. We will try to address the issue if this is still reproducible. Can you share what version of the MATLAB and Synthesis tools used to report this issue?
  1 Comment
Benjamin Granger
Benjamin Granger on 5 Oct 2022
Edited: Benjamin Granger on 5 Oct 2022
Thanks!
I am using MATLAB Version: 9.11.0.1873467 (R2021b) Update 3. The versions of Simulink and HDL Coder are 10.4 and 3.19, respectively.
The synthesis tool is that in Xilinx Vivado 2018.3, with the default Vivado synthesis settings.

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