Verify the Verilog generated by HDLcoder
2 views (last 30 days)
Show older comments
wang on 24 Feb 2023
Answered: Bharath Venkataraman on 24 Feb 2023
I have built the model through Simulink and generated Verilog using HDL Coder. May I ask how to verify Verilog next?
Bharath Venkataraman on 24 Feb 2023
You can use the Generate Testbench feature of HDL Coder to generate an HDL testbench that takes the simulation input and output and constructs an HDL testbench. The HDL code and testbench can run in any HDL simulator of your choice (there are options to generate the required scripts to run the code).
You can also verify the HDL code using a DPIC-C testbench, HDL cosimulation or FPGA-in-the-Loop. These options are described for a Simulink model in this page.
Find more on Code Generation in Help Center and File Exchange
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!Start Hunting!