Integrating HDL QPSK Transmitter and Receiver into Xilinx Vivado
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Hello, I am trying to use a Xilinx Zynq RFSoC to evaluate the above Simulink example using default settings included in the example. However, I know that there are upsample blocks in the code and I am unable to determine what clock frequency to use once I have generated the HDL code. Specifically, I am trying to integrate this for use with the RF Data Converter that Xilinx provides in their RFSoCs. In other words, the example mentions that the HDL is evaluated on a Xilinx Zynq SoC and I would like further guidance on how this is accomplished. Thank you very much.
Kiran Kintali on 6 Oct 2023
HDL QPSK Transmitter and Receiver
This example shows how to implement a QPSK transmitter and receiver in Simulink® that is optimized for HDL code generation and hardware implementation.
The model shown in this example modulates data based on quadrature phase shift keying (QPSK). The goal of this example is to model an HDL QPSK communication system that can transmit and recover information for a real-time system. The receiver implements symbol timing synchronization and carrier frequency and phase synchronization, which are essential in a single-carrier communication system.
HW/SW Co-Design QPSK Transmit and Receive Using Analog Devices AD9361/AD9364
This example shows how to implement wireless communication algorithms on the Zynq® radio platform that are partitioned across the ARM® processing system and the FPGA programmable logic. A QPSK-based communication system is designed for the system.