hdl generated ip stuck at synthesis part in vivado
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Prashanthi Pathipati
on 25 Aug 2023
Commented: Prashanthi Pathipati
on 5 Sep 2023
i have included the generated matlab hdl generated ip in my vivado block design ,but its been stuck at synthesis part,i have tried creating swamp file but it does not work ,could you please help me
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Accepted Answer
Kiran Kintali
on 25 Aug 2023
Consider using resource report to make sure you are at a high level within the limits of the FPGA resources.
sfir_fixed
makehdl('sfir_fixed/symmetric_fir', 'ResourceReport', 'on')
If the algorithm specific resource consumption is within area budgets of your target FPGA consider looking at the critical path estimation report.
>> makehdl('sfir_fixed/symmetric_fir', 'CriticalPathEstimation', 'on')
This can help provide insight into why Vivado Synthesis is not converging.
If you continue to find issues please reach to AMD/Xilinx tech support.
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