Can I control the HDL to/downto designation used for arrays during HDL generation?

I have ports to my system that are fixdt data types with port dimensions greater than 1 (set to 8 in this case). When HDL Coder generates VHDL, it used the "to" direction for my arrays, but I want it to use "downto". Can I control this?

I saw a related post from 2019 with repsect to boolean datatypes that said it cannot be controlled with boolean types and I didn't know if that response also applied to fixdt types or if the functionality had been changed.

https://www.mathworks.com/matlabcentral/answers/490836-hdl-coder-to-downto-order

Answer 1

[Kiran Kintali]

The control is available starting R2023b release for boolean arrays.

https://www.mathworks.com/help/releases/R2023b/hdlcoder/release-notes.html

Generate code for Boolean array with MSB-to-LSB convention

You can now generate code for an array of boolean data in most significant bit (MSB) to least significant bit (LSB) convention. For example, a subsystem with boolean input and output data, the generated VHDL code with the DOWNTO convention has this form:

ENTITY Subsystem IS
PORT ( In1    : IN  std_logic_vector(4 DOWNTO 0); -- boolean [5]
       Out1   : OUT std_logic_vector(4 DOWNTO 0)  -- boolean [5] );
END Subsystem;

You can use this functionality for the VHDL®, Verilog®, and System Verilog target languages.

[Brad Williams]

Does this same capability exist for arrays of std_logic_vector as well? I'm seeing the HDL that my model generates the desired 'downto' port for individual datatypes, but uses 'to' for arrays (where the port diemsions are > 1)

[Kiran Kintali]

Currently it is limited to scalars (integer, fixed-point types in MATLAB) and array of booleans. I will capture this request for the development team.