How to disable clockdriver logic and clr port (automatic added) in generated vhdl code?
2 views (last 30 days)
The dev enviroment of my experiment is Matlab 2020b with Vivavdo 2020.
I attached the sysgen model and relative configuration file. The model is to use HDL coder flow mix ed with sysgen blocks. I placed all sysgen blocks in a subsystem, called sysgen_top, then place in another subsystem called sysgen_module.
The generated hdl code for sysgen_module is correct as block diagram design, i.e., directly connect to sysgen_top.
However, if i go further to check the generated code on sysgen_top. I found the toolchain automatically add "clr" port, which shouldn't exist.
And this port is connected to a module called clock driver. Because I drop the design as external ip in bigger system, the clock driver here is no necessary.
So, I wonder if there's way to disable clock_driver generation, and clr port is not what I want.
Kiran Kintali on 10 Oct 2023
Edited: Kiran Kintali on 10 Oct 2023
This is an integraiton workflow between HDL Coder from MathWorks along with Xilinx System Generator (XSG) from AMD.
In the releases this feature is supported HDL Coder calls system generator under the hood and includes the generated code as a blackbox in the overall HDL Coder generated code.
All customization options are available on the subsystem that houses the XSG blocks. You need to right click on the subsystem and specify the customization options.
Can you please reach out to tech support on what sort of customizations are missing at the subsystem level marked for XSG integration? The feasbility depends on the XSG codegeneration step outside of MathWorks control.