HDL Coder fails to generate VHDL...Assertion Failed With Debug Message: B:\matlab\src\cgir_hdl\hdl_emitters\VHDLPIREmitter.cpp:1715:assignExpr: Component 's output signal
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The following error generated during HDL Code Generation:
Failed Unexpected Error during HDL Code Generation. Contact support@mathworks.com with reproduction steps. Assertion Failed With Debug Message: B:\matlab\src\cgir_hdl\hdl_emitters\VHDLPIREmitter.cpp:1715:assignExpr: Component 's output signal hdlcoder.pirctx/endEmission Unexpected Error during HDL Code Generation. Contact support@mathworks.com with reproduction steps. Assertion Failed With Debug Message: B:\matlab\src\cgir_hdl\hdl_emitters\VHDLPIREmitter.cpp:1715:assignExpr: Component <Component CtxName="pm6l" RefNum="c1164" UserName="(null)" RTTIClass ="class pir::IndexComp" Network="n0"/>'s output signal <Signal CtxName="pm6l" RefNum="s921" UserName="(null)" RTTIClass ="class pir::Signal" Network="n0\> has no name Error in slhdlcoder.HDLCoder/preBackEnd Error in slhdlcoder.HDLCoder/runPIRTransformAndCodegen Error in slhdlcoder.HDLCoder/makehdl Error in downstream.DownstreamIntegrationDriver/runGenerateRTLCodeAndTestbench Error in runGenerateRTLCodeAndTestbench Error in Simulink.ModelAdvisor/executeCheckCallbackFct Error in Simulink.ModelAdvisor/run Error in Simulink.ModelAdvisor/runCheck Error in ModelAdvisor.Node/runTaskAdvisor Error in ModelAdvisor.Node.runtohere>runToBreakpoint Error in ModelAdvisor.Node.runtohere
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