Generate a PWM in FPGA using a customised carrier.

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Hi Kiran
Hope you doing well. I have seen your helpful answers for everyone. However , i have an issue and wish if you can help. I am trying to generate a PWM pulses using Speedgoat model IO334 FPGA. I have to customise an up-down counter ( as a carrier) to compare with a reference signal in order to obtain our PWM signals to drive a convertor. This counter must be HDL supported.
Keywords : Clock cycle of the speed goat is 10 nanos . Resulation can be 2^32-1.
I will appreciate if you can help

Answers (1)

Kiran Kintali
Kiran Kintali on 27 Oct 2023
Edited: Kiran Kintali on 27 Oct 2023
There are several pulse generator blocks in the Simulink library that are on the HDL Coder roadmap for automatic code generation. Please reach out to tech support with your requirements.
% Simulink / Discontinuities / PWM --> Generates gate pulses depending on the input duty cycle
% Simulink / Sources / Pulse Generator --> Generates square pulses at regular intervals
% Simscape / Electrical / Control / Pusle Width Modulation --> Generates pulses to control switching behavior for a three-phase, two-level power converter
In the mean time you may find useful the attached two PWM generator models using math blocks and counters that are fully HDL Coder compatible.
  1 Comment
WAJDI ELSHARIF
WAJDI ELSHARIF on 27 Oct 2023
Hi Kiran
thanks for your email .
I am working on designing a NEW PWM strategy to run 2 and 3 level convertors. This strategy must be run on real time using speedgoat . This technique should use a customised counter or triangle or sawtooth wave . However the PWM blocks provided by Speegoat can not be modified and can not change the carrier shape. Therefore we are trying to build our PWM using HDLand simulink blocks.
Now , I have an issue and I hope you can help. I am trying to generate PWM pulses using the Speedgoat model IO334 FPGA. I have to customise an up-down counter to compare with a reference signal in order to obtain our PWM signals to drive a converter. This counter must be HDL supported.
I will appreciate it if you can help.
best regards

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