How to create this in Simulink? std_logic_vector16 vec[0:3]

I want to create an array that can hold 4 elements, each of which is a 16-bit vector as an input to an IP block so that when I generate ip from a subsystem, the input is std_logic_vector16 vec[0:3] and not one 64-bit vector which is what I get now with hdlcoder when I send the data in as a either a [4,1] or [1,4] 2-D column or row array. How do I do this in Simulink so that the code generated gives me a 4 element fixed point array?

Answer 1

[Angela Cuadros Castiblanco]

Hello Cheri,

If you're generating HDL code from a Simulink subsystem using makehdl, the behavior you're describing is already supported. When you use a vector signal of size [4x1] or [1x4], where each element is a 16-bit fixed-point or integer type, HDL Coder interprets this as a vector of four elements. In the generated VHDL code, this would typically appear as a structure like vector_of_std_logic_vector16(0 TO 3), as shown in the example below:

However, if you're using the IP core generation workflow, the behavior depends on how the ports are mapped. For instance, when a vector port is mapped to an "External Port", HDL Coder flattens the vector into a single std_logic_vector, resulting in a 64-bit wide port (i.e., std_logic_vector(63 downto 0)). This is currenlty expected behavior for external interfaces.

If this doesn't align with what you're seeing or trying to achieve, could you clarify which workflow you're using (e.g., makehdl vs. IP Core Generation workflow)? And if you're using the IP core generation workflow, how are you configuring the interface (e.g., External Port, AXI4)? Additionally, it would be helpful to understand why you're aiming to preserve the vector structure at the boundary and why the makehdl approach does not meet your requirements.

Best,

Angela

[Cheri Anaclerio]

Thank you, Angela. Your answer explains the behaviour I'm seeing. I am in fact mapping to an external port using the IP Core Generation workflow. What I'd really like is a streaming AXI interface that can connect other IP's but I see that IP Core Generation does not offer that option. Do you have any suggestions of a more appropriate interface that will support an array of std_logic_vectors? Thank you.

[Angela Cuadros Castiblanco]

Thank you for the clarification!

Unfortunately, at this time, the IP Core Generation workflow does not support mapping that results in an array of std_logic_vector signals at the IP core boundary like the one you described. However, there are alternative approaches within the workflow that allow you to interface with other streaming IP cores.

The IP Core Generation workflow provides several options for modeling and mapping to an AXI4-Stream interface, depending on your design requirements, as described here. There are two main workflows you might follow:

• Sample-Based Modeling: This approach is suitable when your algorithm processes a continuous stream of samples. You can model the data signal as either a scalar or a vector. However, if you use a vector, the elements will be packed into a single std_logic_vector, similar to what you observed with external ports. In this modeling style, you must explicitly model at least the data and valid signals, following the simplified streaming protocol described in the documentation.
• Frame-Based Modeling: This is appropriate when your algorithm operates on entire frames of data. In this case, the data signals at the DUT (Design Under Test) boundary can be vectors or matrices. HDL Coder will automatically transform these into a streaming interface at the bounday with data, valid, and ready signals, compatible with AXI4-Stream. Note that this style is not suitable if you need to explicitly model the valid and ready signals yourself. Additionally the data signal data type will correspond to the data type of the elements of the vector or matrix you are using as input to your algorithm.

You might also find it helpful to review the documentation on supported interfaces and data types for IP Core Generation. It provides a good overview of what’s possible and links to different pages on how to structure your model accordingly.

Hope this helps!

[Cheri Anaclerio]

Yes, it does. Thank you very much for the information! I will study the links you sugested. Thanks again.