photo

Angela Cuadros Castiblanco

Last seen: 6 days ago |  Active since 2023

Followers: 0   Following: 0

Spoken Languages:
English, Spanish

Statistics

  • Knowledgeable Level 1
  • First Answer

View badges

Feeds

View by

Answered
simulink ip core generation
Hello, To use the AXI4-Stream interface in the IP core generation workflow in HDL Coder, you can model your algorithm to operat...

3 months ago | 0

Answered
AXI-stream interface violates AXI-stream protocol
Hello Alexander, I'd like to provide some clarity on the protocol implementation within our IP core generation workflow. When m...

7 months ago | 0

Answered
Setting Target interface fails in Debug Zynq design using HDL and Embedded coder example.
Hello Vishnu, The error message you're seeing typically appears when a reference design requires certain non-optional interfac...

9 months ago | 1

Answered
HDL Workflow Advisor - Step 3.2 - "Failed Index exceeds the number of array elements. Index must not exceed 2" in hdlturnkey.interface.ChannelBased/connectFrameInterfacePort
Hello, From your description it sounds like you are using the "legacy frame-based modeling" detailed in: https://www.mathwor...

1 year ago | 0

| accepted