HDL workflow Advisor image

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Yu Chen
Yu Chen on 1 Jul 2018
I will use the HDL workflow to do image processing on the FPGA.
How do I input the image will not be a bunch of interfaces?
My image is 2D, how does the test bench code describe it?

Answers (1)

Bharath Venkataraman
Bharath Venkataraman on 2 Jul 2018
This Vision HDL Toolbox page shows the capabilities provided for image processing on an FPGA. If you have the product, try doc visionhdl and look at the examples.
To target your design easily onto an FPGA, the Xilinx Zynq Support package will help.

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