Is it possible to generate a VHDL File from a MATLAB Function that only contains one (clocked) process?

I'm working with the HDL Coder Toolbox and at the moment I'm trying to generate VHDL Code for a simple Finite State Machine (FSM), which is described in a MATLAB Function Block in Simulink. During my research I found the eml_hdl_design_patterns Library. After opening the Library in Simulink and selecting the FSMs directory, I copied the moore_fsm block and pasted it in an empty Simulink model. Then I created a subsystem, that contains the moore_fsm block, in order to generate VHDL Code.

After Code Generation I evaluated the generated VHDL File of the moore_fsm block. The architecture of the VHDL File contained two processes: one clocked process (moore_fsm_1_process) and one combinatorial process (moore_fsm_1_output). The following code is an excerpt of the generated VHDL File (moore_fsm.vhd):

ARCHITECTURE rtl OF moore_fsm IS
  -- Signals
  SIGNAL moore_state_reg                  : unsigned(1 DOWNTO 0);  -- ufix2
  SIGNAL moore_state_reg_next             : unsigned(1 DOWNTO 0);  -- ufix2
BEGIN
  moore_fsm_1_process : PROCESS (clk)
  BEGIN
    IF rising_edge(clk) THEN
      IF reset = '1' THEN
        moore_state_reg <= to_unsigned(16#0#, 2);
      ELSE 
        moore_state_reg <= moore_state_reg_next;
      END IF;
    END IF;
  END PROCESS moore_fsm_1_process;

  moore_fsm_1_output : PROCESS (A, moore_state_reg)
  BEGIN
    moore_state_reg_next <= moore_state_reg;
    CASE moore_state_reg IS
      WHEN "00" =>
        Z <= '1';
        IF ( NOT A) = '1' THEN 
          moore_state_reg_next <= to_unsigned(16#0#, 2);
        ELSE 
          moore_state_reg_next <= to_unsigned(16#1#, 2);
        END IF;
      WHEN "01" =>
        Z <= '0';
        IF ( NOT A) = '1' THEN 
          moore_state_reg_next <= to_unsigned(16#0#, 2);
        ELSE 
          moore_state_reg_next <= to_unsigned(16#1#, 2);
        END IF;
      WHEN "10" =>
        Z <= '0';
        IF ( NOT A) = '1' THEN 
          moore_state_reg_next <= to_unsigned(16#1#, 2);
        ELSE 
          moore_state_reg_next <= to_unsigned(16#2#, 2);
        END IF;
      WHEN "11" =>
        Z <= '1';
        IF ( NOT A) = '1' THEN 
          moore_state_reg_next <= to_unsigned(16#0#, 2);
        ELSE 
          moore_state_reg_next <= to_unsigned(16#2#, 2);
        END IF;
      WHEN OTHERS => 
        Z <= '0';
    END CASE;
  END PROCESS moore_fsm_1_output;
END rtl;

Now I'm wondering if it is possible to change the MATLAB Code of the moore_fsm block in order to generate a VHDL File which only contains one (clocked) process and no combinatorial process. The architecture of the new VHDL File should look like the following code:

ARCHITECTURE rtl OF moore_fsm IS
  -- Signals
  SIGNAL moore_state_reg                  : unsigned(1 DOWNTO 0);  -- ufix2
  SIGNAL moore_state_reg_next             : unsigned(1 DOWNTO 0);  -- ufix2
BEGIN
  moore_fsm_1_process : PROCESS (clk)
  BEGIN
    IF rising_edge(clk) THEN
      IF reset = '1' THEN
        moore_state_reg <= to_unsigned(16#0#, 2);
      ELSE 
        moore_state_reg <= moore_state_reg_next;
        CASE moore_state_reg IS
		  WHEN "00" =>
			Z <= '1';
			IF ( NOT A) = '1' THEN 
			  moore_state_reg_next <= to_unsigned(16#0#, 2);
			ELSE 
			  moore_state_reg_next <= to_unsigned(16#1#, 2);
			END IF;
		  WHEN "01" =>
			Z <= '0';
			IF ( NOT A) = '1' THEN 
			  moore_state_reg_next <= to_unsigned(16#0#, 2);
			ELSE 
			  moore_state_reg_next <= to_unsigned(16#1#, 2);
			END IF;
		  WHEN "10" =>
			Z <= '0';
			IF ( NOT A) = '1' THEN 
			  moore_state_reg_next <= to_unsigned(16#1#, 2);
			ELSE 
			  moore_state_reg_next <= to_unsigned(16#2#, 2);
			END IF;
		  WHEN "11" =>
			Z <= '1';
			IF ( NOT A) = '1' THEN 
			  moore_state_reg_next <= to_unsigned(16#0#, 2);
			ELSE 
			  moore_state_reg_next <= to_unsigned(16#2#, 2);
			END IF;
		  WHEN OTHERS => 
			Z <= '0';
          END CASE;
      END IF;
    END IF;
  END PROCESS moore_fsm_1_process;
END rtl;

Answer 1

[Kiran Kintali]

The current code style is driven by synthesis best practices. Please reach to technical support for additional customization related requirements of the generated HDL code.