hdl coder IO buffer error

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Fahri Gürbüz
Fahri Gürbüz on 19 Jul 2020
Answered: Kiran Kintali on 15 Nov 2021
Hi,
I am creating a model using model based design for motor control. I have generated vhdl code and run implementation in vivado. In the implemenation step, I have had an error shown as below.
[Place 30-188] UnBuffered IOs: clk has following unbuffered loads : Multiply_Add_out1_1_reg[1](FDRE) Multiply_Add_out1_1_reg[2](FDRE) Multiply_Add_out1_1_reg[3](FDRE) Multiply_Add_out1_1_reg[4](FDRE) Multiply_Add_out1_1_reg[5](FDRE) Multiply_Add_out1_1_reg[6](FDRE) mulOutput_1_reg(DSP48E1) Constant15_out1_1_reg[1](FDRE) Delay6_reg_reg[0](FDRE) Delay6_reg_reg[1](FDRE) HDL_Counter1_out1_reg[0](FDRE).....
I think there is a lack of buffer problem. Could anyone can help me in order to overcome this problem.
Thanks in advance..
Fahri
  3 Comments
Walter Roberson
Walter Roberson on 19 Jul 2020
As a lot of people (including me) would not be familiar with the programs involved, it is useful to note that the message is being emitted by vivado rather than HDL Coder.
It is not obvious to me that vivado is "running out" of buffers; the message could indicate that what is being sent to vivado has some signal chains that are not tied to a clock when they need to be.

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Answers (1)

Kiran Kintali
Kiran Kintali on 15 Nov 2021
Answering the question without access to the model or the full context here.
You could consider enabling the resource utilization report and check resource utilization after code generation and see if anything looks off limits.
sfir_fixed
hdlset_param('sfir_fixed','ResourceReport','on')
makehdl('sfir_fixed/symmetric_fir')

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