hdl coder IO buffer error
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I am creating a model using model based design for motor control. I have generated vhdl code and run implementation in vivado. In the implemenation step, I have had an error shown as below.
[Place 30-188] UnBuffered IOs: clk has following unbuffered loads : Multiply_Add_out1_1_reg(FDRE) Multiply_Add_out1_1_reg(FDRE) Multiply_Add_out1_1_reg(FDRE) Multiply_Add_out1_1_reg(FDRE) Multiply_Add_out1_1_reg(FDRE) Multiply_Add_out1_1_reg(FDRE) mulOutput_1_reg(DSP48E1) Constant15_out1_1_reg(FDRE) Delay6_reg_reg(FDRE) Delay6_reg_reg(FDRE) HDL_Counter1_out1_reg(FDRE).....
I think there is a lack of buffer problem. Could anyone can help me in order to overcome this problem.
Thanks in advance..
Kiran Kintali on 15 Nov 2021
Answering the question without access to the model or the full context here.
You could consider enabling the resource utilization report and check resource utilization after code generation and see if anything looks off limits.