How to implement a 3D Lookup Table that can be converted with HDL Coder?
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Dominik Hiltbrunner
on 1 Sep 2020
Commented: Dominik Hiltbrunner
on 4 Sep 2020
Hello Community
I want to implement a non-linear function with 3 variables, i.e. f(x,y,z), in Simulink and convert it to VHDL code using HDL coder.
Since I avoid division blocks I implement non-linear functions with Lookup Tables. However, although there is a n-D Lookuptable in Simulink's HDL coder library, it does not support this block for code generation. I get an error saying that only 1D and 2D Lookup Tables are supportet.
Is there a workaround for this? My function is in the form of
where are constants and are unsigned integers from 0 to 31 (5 bit binary inputs), yielding a 32x32x32 Lookup Table.
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Accepted Answer
Kiran Kintali
on 3 Sep 2020
Edited: Kiran Kintali
on 3 Sep 2020
Can you consider the following modeling workaround until 3D LUT table support is available in HDL Coder?
More Answers (2)
Kiran Kintali
on 2 Sep 2020
3D LUT support is on the HDL Coder near term product roadmap and will be available in an upcoming release.
In the interim we can guide you build such a model using supported blocks. Could your share the sample model (that generated the error) with the algorithm requirements shown in the question?
Are you planning to do fixed-point or floating-point model? What are the data types and interpolation options under consideration? What is your target FPGA and QoR (power, performance, area requirements)?
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