Timed out on waiting for AXI write response.

After successfully running the HDLWA via the JTAG route, i create an AXI master object in MATLAB and then i try and write to memory to a specific register but i get an error as follow:

h.writememory(hex2dec('A4000100'), 6)

Error using fpgadebug_mex

Timed out on waiting for AXI write response. The aresetn signal on the MATLAB AXI Master IP is stuck at active low.

Error in hdlverifier.AXIMasterJTAG/writememory

I am not sure if it's my setup in Vivado that's incorrect but would appreacite any guidance/help on this error.

I am using R2020a with Vivado version 2018.2. Windows 10 OS, the model is built in Simulink and I created a custom reference deign. I use the HDLWA to create an IP Core that fits into a larger design. The JTAG is a USB 2.0 type A to type B an the board settings were changed to use this configuration. I am using the Blining LED example in Simulink.

Answer 1

[Kiran Kintali]

This is insufficient info to answer the question. Someone to answer this question would need to know the following details at the minimum to sufficently diagnose the issue you are facing.

• What version of HDL Coder and HDL Verifier are you using?
• Are using MATLAB only workflow or is it reproducible in Simulink as well?
• Are you using Vivado? What release?
• Are you specifically target a off-the-shlef board? If so details would be useful
• Are you using MathWorks supplied reference design or did you build you own?
• What is your platform (Windows/Linux)?
• What kind of JTAG cable?
• Have you tried any shipping examples? Do you see the same behavior?
• I am sure I missed few others here...

[Praneet Kala]

I am using R2020 with Vivado version 2018.2. Windows 10 OS, the model is built in Simulink and I created a custom reference deign. I use the HDLWA to create an IP Core that fits into a larger design. The JTAG is a USB 2.0 type A to type B an the board settings were changed to use this configuration. I am using the Blining LED example in Simulink.

[Kiran Kintali]

I understand you are using custom board. can you check if running the design on one of the evaluation boards also shows the same issue?

[Praneet Kala]

It seems to work on another eval board so the problem lies with th register that i am using. I will have to re-assign and generate a new bitstream and test again.

[Nadatimuj]

@Praneet Kala Did you find a solution on this? I am also trying to write to a register with Matlab AXI master and getting the exact same error.

writememory(mem, 0,100)

Error using fpgadebug_mex

Timed out on waiting for AXI write response. The aresetn signal on the MATLAB AXI Master IP is stuck at active low.

Error in hdlverifier.AXIMasterJTAG/writememory

[Praneet Kala]

Hi Navid

With regards to the active low state, it was due to the SD Card config. I had to just use the boot.bin on the configurable partition on the SD card. What was happening is the ARM processor kept on resetting and i didn't have the the MW config set up (I didn't use the MathWorks buildroot). I also didn't use EC (Embedded Coder) and was following the old FPGA route only.

This is something you need to look at in detail when it comes to SoC development. The SD Card image and contents is proably the most effort and work. The MATLAB side of things is easy :).

I hope this answers your questions and guides you to debugging it.

[Nadatimuj]

Hi @Praneet Kala Thanks for your quick response. I am not using any SD card. My Kintex Ultrascale KU040 board is connnected to my PC with a micro USB cable through the on-board Digilent USB-JTAG module. I used this for programming and also using this for writing data. My board doesn't have any SoC too. I am just trying to write to a memory mapped slave register through the AXI master. I am attaching my project as well as a screenshot of the block design. You can also download my project: https://drive.google.com/file/d/1M9Cedvr442VkiHGPODFa4UxSA7h5vV2l/view?usp=sharing

If you can suggest anything that would be really helpful. I am stuck for 2 days.

Answer 2

[Nadatimuj]

@Praneet Kala My issue is solved here: https://forums.xilinx.com/t5/Xilinx-Evaluation-Boards/Why-is-output-of-clock-wizard-stuck-to-zero/td-p/1211214

My issue was, I didn't use crystal clock. I used create_clock only as the Matlab documentation showed. Using differential crystal clock solved my problem.

Thanks for your help.