When you select "Coprocessing -- Blocking mode", HDL Coder generates two synchronization registers in your IP core for start/end of the FPGA processing:
- IPCore_Strobe: The processor should write 1 to bit 0 of this register after it has written all the input data to the FPGA. This triggers the FPGA to begin execution for one DUT subsystem sample time.
- IPCore_Ready: The processor should wait until bit 0 of this register is 1 before reading output data from the FPGA. The FPGA sets this register to 1 when it finishes execution for one DUT subsystem sample time.
The addresses for these registers can be found in the generated IP core report.