Processor and FPGA Synchronization in Coprocessing Mode

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Hello everyone.
I'm following this documentation to run an experiment that is hardware-in-the-loop:
Sicne the FPGA is very fast compared to the processor, I chose the coprocessing mode (blocking) for syncronization. The documentation states the following: "During each sample time, the processor writes to the FPGA, then stops and waits for an indication that the FPGA has finished processing before continuing to run."
However, I do not know what is this indication that the FPGA has finished. My problem is that the processor reads the FPGA before it has finished, and I can't find any clue for giving the FPGA more time to finish.
Thank you very much.

Accepted Answer

JT Ferrara
JT Ferrara on 7 Jul 2021
Hi Joaquin,
When you select "Coprocessing -- Blocking mode", HDL Coder generates two synchronization registers in your IP core for start/end of the FPGA processing:
  1. IPCore_Strobe: The processor should write 1 to bit 0 of this register after it has written all the input data to the FPGA. This triggers the FPGA to begin execution for one DUT subsystem sample time.
  2. IPCore_Ready: The processor should wait until bit 0 of this register is 1 before reading output data from the FPGA. The FPGA sets this register to 1 when it finishes execution for one DUT subsystem sample time.
The addresses for these registers can be found in the generated IP core report.

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