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how to report time-scale of simulink model

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dayu lai
dayu lai on 29 Jul 2021
Commented: dayu lai on 30 Jul 2021
I am using HDL coder to generate RTL from simulink model.
As you know, it is import to assign time-scale of port in simulink model, which defines the clock rate of one module.
However, in my design there will be multiple time-scale. Some module works under tsa, some module works under tsb. Usually, I would like to assign time-scale at the very begining of a signal path, while others will inherit from its previous point, until the time-scale is changed. At this time, I will assign a new time-scale at the begining of a new clock rate module.
My question is is there a way to report all the time scale of each modules? The aim is to verify if I give them the correct clock rate or the clock domain of each module is correct.
Thanks a lot!

Answers (1)

Bharath Venkataraman
Bharath Venkataraman on 29 Jul 2021
If you set the sample times on the sources such that the HDL Subsystem sees different Simulink rates, that will convey the right information on the timescale for each block.
You can also change sample times using the Downsample, Upsample, Repeat or Rate Transition blocks.
Bharath Venkataraman
Bharath Venkataraman on 30 Jul 2021
You can turn on sample time colors and view a legend for those colors. This page has more information. Does this help?

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