How to store the output of a repeating function (Matlab Function Block Simulink) ?

I was trying out the Self guided tutorial to implement a hardware friendly peak-finder. (https://www.mathworks.com/matlabcentral/fileexchange/69651-hdl-coder-self-guided-tutorial)

The function block takes 11 samples at a time and compares those with the middle sample and if theyre smaller, then it is a local max.

when it is detected the detected flag goes up (detected = true),but it doesnt show the location where the detected=true.

the function runs multiple times, until the inputs dont change and there is only one time where a peak is detected, .

I want to find out where this peak is located .

I implemented a persistent counter so every time the function runs it adds +1 to the counter, and that one time where detected is true, that is the location (+/- a constant). So its a basic if condition:

if detected==true
peak_loc=counter;
end

the problem is i need to assign the function output (peak_loc) in the else condition also, but this overwrites the variable the next time the function runs, because the peak was detected in the previous function run.

Can somebody help?

(My idea was to store these function outputs in an array and then find the position of the ''true'' and that will be the peak location, but there will also be the problem of the else condition)

Answer 1

[Kiran Kintali]

% Hardware friendly implementation of peak finder

%

% Function inputs:

% * WindowLen - non-tunable parameter defined under Simulink->Edit Data

% * threhold - input port (connected to constant)

% * DataBuff - input port (buffering done using Simulink block)

%

% Function outputs:

% * "detected" is set when MidSample is local max

% * "index" 64bit index value that holds the location of the peak when detected is high

function [MidSample,detected,index] = fcn(WindowLen, threshold, DataBuff)

%#codegen

persistent counter;

if isempty(counter)

counter = uint64(0);

end

counter = counter + 1;

index = counter;

MidIdx = ceil(WindowLen/2);

% Compare each value in the window to the middle sample via subtraction

MidSample = DataBuff(MidIdx);

CompareOut = DataBuff - MidSample; % this is a vector

% if all values in the result are negative and the middle sample is

% greater than a threshold, it is a local max

if all(CompareOut <= 0) && (MidSample > threshold)

detected = true;

else

detected = false;

end

[Youssef Abdelsalam]

First of all thank you so much for your answer,your idea is much easier and faster (less space and time) than mine. :-)

But The counter = uint64(0); part gave me the following error: Data 'tmp': int64 and uint64 inputs or outputs are not supported in Simulink and Stateflow. Cast 'tmp' to a supported numeric type instead. (I named it tmp instead of index).

Any idea what i can do here ?

Is this model synthesizable ? (because i need to implement it on an FPGA (XILINX ARTIX-7) )

[Youssef Abdelsalam]

...And does this algorithm support finding multiple peaks not just one ?

Answer 2

[Kiran Kintali]

>> makehdl('pulse_detector_v4_with_index/Pulse Detector')
### Generating HDL for 'pulse_detector_v4_with_index/Pulse Detector'.
### Using the config set for model pulse_detector_v4_with_index for HDL code generation parameters.
### Running HDL checks on the model 'pulse_detector_v4_with_index'.
### Begin compilation of the model 'pulse_detector_v4_with_index'...
### Applying HDL optimizations on the model 'pulse_detector_v4_with_index'...
### Begin model generation.
### Model generation complete.
### Begin VHDL Code Generation for 'pulse_detector_v4_with_index'.
### Working on pulse_detector_v4_with_index/Pulse Detector/Compute Power as hdl_prj\hdlsrc\pulse_detector_v4_with_index\Compute_Power.vhd.
### Working on pulse_detector_v4_with_index/Pulse Detector/Local Peak/MATLAB Function as hdl_prj\hdlsrc\pulse_detector_v4_with_index\MATLAB_Function.vhd.
### Working on pulse_detector_v4_with_index/Pulse Detector/Local Peak as hdl_prj\hdlsrc\pulse_detector_v4_with_index\Local_Peak.vhd.
### Working on pulse_detector_v4_with_index/Pulse Detector/Discrete FIR Filter HDL Optimized/FilterBank/FilterCoef as hdl_prj\hdlsrc\pulse_detector_v4_with_index\FilterCoef.vhd.
### Working on pulse_detector_v4_with_index/Pulse Detector/Discrete FIR Filter HDL Optimized/FilterBank/FilterCoef as hdl_prj\hdlsrc\pulse_detector_v4_with_index\FilterCoef_block.vhd.
### Working on pulse_detector_v4_with_index/Pulse Detector/Discrete FIR Filter HDL Optimized/FilterBank/FilterCoef as hdl_prj\hdlsrc\pulse_detector_v4_with_index\FilterCoef_block1.vhd.
### Working on pulse_detector_v4_with_index/Pulse Detector/Discrete FIR Filter HDL Optimized/FilterBank/subFilter/FilterTapSystolicWvldin as hdl_prj\hdlsrc\pulse_detector_v4_with_index\FilterTapSystolicWvldin.vhd.
### Working on pulse_detector_v4_with_index/Pulse Detector/Discrete FIR Filter HDL Optimized/FilterBank/subFilter as hdl_prj\hdlsrc\pulse_detector_v4_with_index\subFilter.vhd.
### Working on pulse_detector_v4_with_index/Pulse Detector/Discrete FIR Filter HDL Optimized/FilterBank as hdl_prj\hdlsrc\pulse_detector_v4_with_index\FilterBank.vhd.
### Working on pulse_detector_v4_with_index/Pulse Detector/Discrete FIR Filter HDL Optimized as hdl_prj\hdlsrc\pulse_detector_v4_with_index\Discrete_FIR_Filter_HDL_Optimized.vhd.
### Working on pulse_detector_v4_with_index/Pulse Detector as hdl_prj\hdlsrc\pulse_detector_v4_with_index\Pulse_Detector.vhd.
### Generating package file hdl_prj\hdlsrc\pulse_detector_v4_with_index\Pulse_Detector_pkg.vhd.
### Code Generation for 'pulse_detector_v4_with_index' completed.
### Generating HTML files for code generation report at pulse_detector_v4_with_index_codegen_rpt.html
### Creating HDL Code Generation Check Report Pulse_Detector_report.html
### HDL check for 'pulse_detector_v4_with_index' complete with 0 errors, 0 warnings, and 2 messages.
### HDL code generation complete.

>> makehdl('pulse_detector_v4_with_index/Pulse Detector', 'targetlang', 'verilog')
### Generating HDL for 'pulse_detector_v4_with_index/Pulse Detector'.
### Using the config set for model pulse_detector_v4_with_index for HDL code generation parameters.
### Running HDL checks on the model 'pulse_detector_v4_with_index'.
### Begin compilation of the model 'pulse_detector_v4_with_index'...
### Begin model generation.
### Model generation complete.
### Begin Verilog Code Generation for 'pulse_detector_v4_with_index'.
### Working on pulse_detector_v4_with_index/Pulse Detector/Compute Power as hdl_prj\hdlsrc\pulse_detector_v4_with_index\Compute_Power.v.
### Working on pulse_detector_v4_with_index/Pulse Detector/Local Peak/MATLAB Function as hdl_prj\hdlsrc\pulse_detector_v4_with_index\MATLAB_Function.v.
### Working on pulse_detector_v4_with_index/Pulse Detector/Local Peak as hdl_prj\hdlsrc\pulse_detector_v4_with_index\Local_Peak.v.
### Working on pulse_detector_v4_with_index/Pulse Detector/Discrete FIR Filter HDL Optimized/FilterBank/FilterCoef as hdl_prj\hdlsrc\pulse_detector_v4_with_index\FilterCoef.v.
### Working on pulse_detector_v4_with_index/Pulse Detector/Discrete FIR Filter HDL Optimized/FilterBank/FilterCoef as hdl_prj\hdlsrc\pulse_detector_v4_with_index\FilterCoef_block.v.
### Working on pulse_detector_v4_with_index/Pulse Detector/Discrete FIR Filter HDL Optimized/FilterBank/FilterCoef as hdl_prj\hdlsrc\pulse_detector_v4_with_index\FilterCoef_block1.v.
### Working on pulse_detector_v4_with_index/Pulse Detector/Discrete FIR Filter HDL Optimized/FilterBank/subFilter/FilterTapSystolicWvldin as hdl_prj\hdlsrc\pulse_detector_v4_with_index\FilterTapSystolicWvldin.v.
### Working on pulse_detector_v4_with_index/Pulse Detector/Discrete FIR Filter HDL Optimized/FilterBank/subFilter as hdl_prj\hdlsrc\pulse_detector_v4_with_index\subFilter.v.
### Working on pulse_detector_v4_with_index/Pulse Detector/Discrete FIR Filter HDL Optimized/FilterBank as hdl_prj\hdlsrc\pulse_detector_v4_with_index\FilterBank.v.
### Working on pulse_detector_v4_with_index/Pulse Detector/Discrete FIR Filter HDL Optimized as hdl_prj\hdlsrc\pulse_detector_v4_with_index\Discrete_FIR_Filter_HDL_Optimized.v.
### Working on pulse_detector_v4_with_index/Pulse Detector as hdl_prj\hdlsrc\pulse_detector_v4_with_index\Pulse_Detector.v.
### Code Generation for 'pulse_detector_v4_with_index' completed.
### Generating HTML files for code generation report at pulse_detector_v4_with_index_codegen_rpt.html
### Creating HDL Code Generation Check Report Pulse_Detector_report.html
### HDL check for 'pulse_detector_v4_with_index' complete with 0 errors, 0 warnings, and 2 messages.
### HDL code generation complete.
>> 

I am not seeing the error w.r.to code generator. What version of MATLAB are you using?

You can update "detected" logic in the MATLAB code to enable other scenerios.

Yes, you should be able to synthesize this code using synthesis tool to target FPGA / ASIC.

[Youssef Abdelsalam]

I am using version R2019a

[Youssef Abdelsalam]

Thanks again for your answer !

[Youssef Abdelsalam]

Quick update: I upgraded the Matlab version (from 2019a to 2021a) and it worked.

Apparently this "type-casting" wasnt supported in the 2019a version.

Thanks a lot for your help ! :-)

[Youssef Abdelsalam]

Do you have an idea how to detect multiple peaks not just one ? If i play with the threshold, the detected variable finds other peaks but it displays only the location and value of the last peak it detected

[Youssef Abdelsalam]

Another question: if i am using FPGA Data capture to capture the data from the FPGA with DSP System Toolbox Logic Analyzer, do i need the index output ? (Because with the Logic Analyzer i'd see where the detected=1 and i'd locate it manually) .

Answer 3

[Kiran Kintali]

>> Do you have an idea how to detect multiple peaks not just one ?

Can you consider Multiple enabled delays in a cascaded fashion to store more peaks?