Steven Hatcher
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Team Lead for the HDL Coder Optimizations area.
C++, MATLAB, VHDL
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HDL-Coder Delay Balancing in Feedback-Loop workaround
Hi Niklas, There is an optimization that can leverage a faster clock in regions of logic running at a slower rate. It looks lik...
2 years ago | 0
| accepted
Enabled Subsystem produce hold without bypass
Hi Andrew, The only way this style of code can be generated which avoids creation of the by-pass register is to have a delay at...
2 years ago | 0
Multiply and add not correctly mapping to a single DSP slice
Hi Justin, Are any of the adders using saturation or rounding logic that a Xilinx DSP48E1 would not natively support? Looking a...
2 years ago | 0