Answered

Code Generation for d flipflop

Do you really need to model the D Flip Flop (especially the clock)? If not, I suggest using the Delay block (with enable if you ...

Code Generation for d flipflop

Do you really need to model the D Flip Flop (especially the clock)? If not, I suggest using the Delay block (with enable if you ...

1 year ago | 0

| accepted

Answered

Error evaluating 'InitFcn' callback of block_diagram 'hdlcoder_lteofdm_modDetect'. Callback string is 'simParams = hdlcoder_lteofdm_modDetectref_init; simParams = hdlcoder_lteofdm_modDetecthdl_init(simParams);

As John mentioned in the comments, the function mentioned in the Diagnosic Viewer, lteTestModel, is a function in the LTE Toolbo...

Error evaluating 'InitFcn' callback of block_diagram 'hdlcoder_lteofdm_modDetect'. Callback string is 'simParams = hdlcoder_lteofdm_modDetectref_init; simParams = hdlcoder_lteofdm_modDetecthdl_init(simParams);

As John mentioned in the comments, the function mentioned in the Diagnosic Viewer, lteTestModel, is a function in the LTE Toolbo...

1 year ago | 0

| accepted

Answered

Enable Not Working on Synchronous Subsystem

The synchronous state control behaves exactly like the HDL would, doing a divide by zero because the reciprocal block is a combi...

Enable Not Working on Synchronous Subsystem

The synchronous state control behaves exactly like the HDL would, doing a divide by zero because the reciprocal block is a combi...

1 year ago | 0

| accepted

Answered

Test bench can't work for some 'entity' are not compiled in library 'xil_defaultlib'.

System Generator is a third-party blockset provided by Xilinx. For any further questions, please contact Xilinx technical suppor...

Test bench can't work for some 'entity' are not compiled in library 'xil_defaultlib'.

System Generator is a third-party blockset provided by Xilinx. For any further questions, please contact Xilinx technical suppor...

1 year ago | 0

Answered

Dose HDL coder generate Verilog HDL-1995 verision or Verilog HDL-2001 version？

HDL Coder generates HDL code compliant with Verilog-2001. https://www.mathworks.com/help/hdlcoder/gs/language-and-tool-version-...

Dose HDL coder generate Verilog HDL-1995 verision or Verilog HDL-2001 version？

HDL Coder generates HDL code compliant with Verilog-2001. https://www.mathworks.com/help/hdlcoder/gs/language-and-tool-version-...

1 year ago | 1

Answered

How to get fractional delay filter in vhdl using matlab 2021a.

You can look at this example that shows how to quantize the filter before generating HDL.

How to get fractional delay filter in vhdl using matlab 2021a.

You can look at this example that shows how to quantize the filter before generating HDL.

1 year ago | 0

Answered

Why is my FFT HDL Optimized block running slower in FIL than Simulink?

This slowdown is due to the time it takes to send the data over from Simulink to the FPGA and back. You can use an Ethernet cab...

Why is my FFT HDL Optimized block running slower in FIL than Simulink?

This slowdown is due to the time it takes to send the data over from Simulink to the FPGA and back. You can use an Ethernet cab...

1 year ago | 0

| accepted

Answered

using bandpass filter on waveform

You can use the fdesign.bandpass function to design the filter. The resulting FIR or Biquad Filter can be used to generate HDL c...

using bandpass filter on waveform

You can use the fdesign.bandpass function to design the filter. The resulting FIR or Biquad Filter can be used to generate HDL c...

1 year ago | 1

Answered

i m trying using converting signal processing block into hdl code , but some of the blocks are not compatible into hdl conversion .does anyone knows how to do it

Please check the Code Generation examples in Phased Array System Toolbox. The HDL code generation examples show how to implement...

i m trying using converting signal processing block into hdl code , but some of the blocks are not compatible into hdl conversion .does anyone knows how to do it

Please check the Code Generation examples in Phased Array System Toolbox. The HDL code generation examples show how to implement...

1 year ago | 0

| accepted

Answered

Changing HDL FIR filter numerator while simulation is running

You can set the property Coefficients Source to input port and feed the coefficients via the input port. This will allow you to ...

Changing HDL FIR filter numerator while simulation is running

You can set the property Coefficients Source to input port and feed the coefficients via the input port. This will allow you to ...

1 year ago | 0

Answered

IIR Filter Coefficant Value

Click on File -> Export. There is an option to export the coefficients to the workspace (SOS, G will be exported as variables ac...

IIR Filter Coefficant Value

Click on File -> Export. There is an option to export the coefficients to the workspace (SOS, G will be exported as variables ac...

1 year ago | 0

Answered

Is matlab R2020a compatible with the latest xilinx system generator 2019.1?

I believe the answer is no. The question has been answered in this post.

Is matlab R2020a compatible with the latest xilinx system generator 2019.1?

I believe the answer is no. The question has been answered in this post.

1 year ago | 0

Answered

Hi, I am using R2014b but cant find the HDL code in Code menu, only C/C++ code. what should i do to genarate a HDLcode for my simulink model.

You likely do not have HDL Coder installed. Type ver at the MATLAB command prompt to see if you have HDL Coder installed.

Hi, I am using R2014b but cant find the HDL code in Code menu, only C/C++ code. what should i do to genarate a HDLcode for my simulink model.

You likely do not have HDL Coder installed. Type ver at the MATLAB command prompt to see if you have HDL Coder installed.

1 year ago | 1

| accepted

Answered

Do Enabled Subsystems use multiplexers in generated HDL code?

In order to get different rates, either through clock enables or through multiple clocks, you need to model the signals at diffe...

Do Enabled Subsystems use multiplexers in generated HDL code?

In order to get different rates, either through clock enables or through multiple clocks, you need to model the signals at diffe...

1 year ago | 0

Answered

'/Serializer1D/HDL1DSe' error occurred when invoking 'getOutputSizeImpl' method of 'hdl.serializer1D'

I was able to avoid the error by setting the dimension of inputA to 1. Model attached.

'/Serializer1D/HDL1DSe' error occurred when invoking 'getOutputSizeImpl' method of 'hdl.serializer1D'

I was able to avoid the error by setting the dimension of inputA to 1. Model attached.

1 year ago | 0

| accepted

Answered

How can I get the input names of the first level only in my simulink model?

You can use the SearchDepth parameter to specify the depth of the search. sysIns = find_system(bdroot,'SearchDepth',1, 'BlockT...

How can I get the input names of the first level only in my simulink model?

You can use the SearchDepth parameter to specify the depth of the search. sysIns = find_system(bdroot,'SearchDepth',1, 'BlockT...

1 year ago | 0

| accepted

Answered

Warning: the font "Times" is not available, so "Lucida Bright" has been substituted, but may have unexpected appearance or behavor. Re-enable the "Times" font to remove this

What operation are you trying to eprform? Are you trying to generate HDL Code? If yes, do you have HDL Coder installed and lice...

Warning: the font "Times" is not available, so "Lucida Bright" has been substituted, but may have unexpected appearance or behavor. Re-enable the "Times" font to remove this

What operation are you trying to eprform? Are you trying to generate HDL Code? If yes, do you have HDL Coder installed and lice...

1 year ago | 0

Answered

I am trying to run the Xilinx Demo in simulating but I get "Error in 'sysgenSSRIFFT/I.IM': Initialization commands cannot be evaluated."

"System Generator for DSP" is a third-party blockset provided by Xilinx. For questions related to System Generator, please conta...

I am trying to run the Xilinx Demo in simulating but I get "Error in 'sysgenSSRIFFT/I.IM': Initialization commands cannot be evaluated."

"System Generator for DSP" is a third-party blockset provided by Xilinx. For questions related to System Generator, please conta...

1 year ago | 0

Answered

HDL coder sharing factor and axi-stream valid signal

I will likely need a little more information on exactly which FIR block you are using, but you can put in a sharing factor on th...

HDL coder sharing factor and axi-stream valid signal

I will likely need a little more information on exactly which FIR block you are using, but you can put in a sharing factor on th...

1 year ago | 0

Answered

Is the DSP Builder for Intel FPGAs compatible with the Computer Vision Toolbox?

Did you mean to ask about Vision HDL Toolbox and not Computer Vision Toolbox? In that case, the HDL code you generate from Visio...

Is the DSP Builder for Intel FPGAs compatible with the Computer Vision Toolbox?

Did you mean to ask about Vision HDL Toolbox and not Computer Vision Toolbox? In that case, the HDL code you generate from Visio...

1 year ago | 1

Answered

How to change frequency of sine wave on FPGA IO334?

One way to do this is by using the NCO HDL Optimized block and change the phase increment. Here is an example of how to use the ...

How to change frequency of sine wave on FPGA IO334?

One way to do this is by using the NCO HDL Optimized block and change the phase increment. Here is an example of how to use the ...

1 year ago | 0

Answered

Matlab Implementation on Hardware Devices

Here is an example of how to go from MATLAB code to generating HDL code using Vision HDL Toolbox. You can then use the Vision H...

Matlab Implementation on Hardware Devices

Here is an example of how to go from MATLAB code to generating HDL code using Vision HDL Toolbox. You can then use the Vision H...

1 year ago | 0

Answered

How to switch to visualize the output of FFT HDL Optimized in the frequency domain ?

If you did this in Simulink, you can send the output of the Simulink subsystem to the Spectrum Analyzer and do the analysis ther...

How to switch to visualize the output of FFT HDL Optimized in the frequency domain ?

If you did this in Simulink, you can send the output of the Simulink subsystem to the Spectrum Analyzer and do the analysis ther...

2 years ago | 0

Answered

Why FFT HDL Optimized has not output?

It looks like the input valid is not being set to the right pulse width to feed in all the input data for a given frame. Please ...

Why FFT HDL Optimized has not output?

It looks like the input valid is not being set to the right pulse width to feed in all the input data for a given frame. Please ...

2 years ago | 0

Answered

Why is the output of the FFT HDL Optimized block zeros in Vivado's Simulation ?

I'd first suggest that you run the generated HDL and Testbench to make sure that the HDL design is working correctly. The next ...

Why is the output of the FFT HDL Optimized block zeros in Vivado's Simulation ?

I'd first suggest that you run the generated HDL and Testbench to make sure that the HDL design is working correctly. The next ...

2 years ago | 0

| accepted

Answered

How to implement a real-time fft for FPGA with matlab or simulink ?

The HDL code from the FFT HDL Optimized does do processing in real-time with streaming samples. It also allows you to process mu...

How to implement a real-time fft for FPGA with matlab or simulink ?

The HDL code from the FFT HDL Optimized does do processing in real-time with streaming samples. It also allows you to process mu...

2 years ago | 0

| accepted

Answered

MATLAB function block doesn't generate synthesizable HDL.

It appears that you have floating point values in your MATLAB code. If you want to retain floating point numerics for your HDL,...

MATLAB function block doesn't generate synthesizable HDL.

It appears that you have floating point values in your MATLAB code. If you want to retain floating point numerics for your HDL,...

2 years ago | 0

Answered

Synthesizable VHDL code for filter design (using FDATOOL) not obtained for MATLAB R2015a

This is becasuse the filter is not quantized. Use the Quantization panel in fdatool to create a fixed-point biquad filter. If y...

Synthesizable VHDL code for filter design (using FDATOOL) not obtained for MATLAB R2015a

This is becasuse the filter is not quantized. Use the Quantization panel in fdatool to create a fixed-point biquad filter. If y...

2 years ago | 0

Answered

how to report time-scale of simulink model

If you set the sample times on the sources such that the HDL Subsystem sees different Simulink rates, that will convey the right...

how to report time-scale of simulink model

If you set the sample times on the sources such that the HDL Subsystem sees different Simulink rates, that will convey the right...

2 years ago | 0

Answered

How do i design a synthesizable FFT with Simulink or Matlab for later on FPGA Implementation ?

The examples in this page should be a good start for you to design the input and generate hdl code.

How do i design a synthesizable FFT with Simulink or Matlab for later on FPGA Implementation ?

The examples in this page should be a good start for you to design the input and generate hdl code.

2 years ago | 1